IFPA300 Datasheet, PDF (1/2 Pages) InterFET Corporation – Monolithic JFET Preamplifier

x
IFPA300, IFPA301
Monolithic JFET Preamplifier
Description & Features
The IFPA300 series is an inverting transimpedance
amplifier featuring extremely low noise and a wide
gain-bandwidth suitable as a charge-sensitive pre-
amplifier for a broad range of applications.
The monolithic IFPA300 series contain 8 n-channel
epitaxial-channel diffused-gate JFETs to achieve
optimally low 1/f noise performance over a wide
temperature range (120K-300K).
DC open loop gain
GBW
e¯_N @ 10 Hz
85 dB
200 MHz
3.0 nV/√Hz
General Specifications
Power Dissipation at VDD = 12 V
<100 mW
Input Leakage Current (T = 300 K)
10 pA
Input-Referred Noise Voltage (f = 10 kHz)
0.6 nV/√Hz
Input-Referred Noise Voltage (f = 10 Hz)
3.0 nV/√Hz
Output Range at VDD = 12 V
4.0 V (5.0 V Max)
Designed to drive 50Ω load.
Charge Sensitive
Preamplifier Specifications
The IFPA300 Series is actually tailored to detector
capacitance in the 100 Ð 1000 pF range.
Input Open-Loop Capacitance
60 pF
Rise Time (CD = 500 pF, Cf = 33 pF)
20 ns
Equivalent Noise Charge
(Measured with semigaussian shaping, peaking
time = t_p)
4200 e– rms at CD @ 500 pF, t_p = 0.2 µm
3200 e– rms at CD @ 500 pF, t_p = 1.0 µm
4200 e– rms at CD @ 500 pF, t_p = 4.0 µm
01/99
Absolute maximum ratings at TA = 25°C
All pins (except Input) referenced to Bias 3
85 dB
Input to Bias 3
ØV
Power Dissipation
225 mW
Derating Factor
1.8 mW/°C
Operating Temperature
150°C
At this time, there are two units in this family.
The 300/301 Series gives more flexibility with respect
to output transistor drain.
The 310/311 Series ties the output transistor drain to
the V_DD line.
Simplified Schematic Circuit
Bias 1
Bias 2
Input
J₄
V_DD
J₇
Substrate
J₃
Open
J₈
Drain
Output
J₂
J₆
J₁
J₅
Open
Source
Output
Bias 3
V_SS
Packages & Test Circuit Overside
1000 N. Shiloh Road, Garland, TX 75042
[phone] FAX [phone]
www.interfet.com