8XC196MD Datasheet, PDF (9/25 Pages) Intel Corporation – INDUSTRIAL MOTOR CONTROL MICROCONTROLLER

8XC196MD
PIN DESCRIPTIONS (Alphabetically Ordered)
Symbol
Function
ACH0 – ACH13
(P0 0–P0 7 P1 0–P1 5)
Analog inputs to the on-chip A D converter ACH0 – 7 share the input pins
with P0 0–7 and ACH8 – 13 share pins with P1 0 – 5 If the A D is not used
the port pins can be used as standard input ports
ANGND
ALE ADV(P5 0)
Reference ground for the A D converter Must be held at nominally the
same potential as V_SS
Address Latch Enable or Address Valid output as selected by CCR Both
options allow a latch to demultiplex the address data bus on the signal’s
falling edge When the pin is ADV it goes inactive (high) at the end of the
bus cycle ALE ADV is active only during external memory accesses Can be
used as standard I O when not used as ALE ADV
BHE WRH (P5 5)
Byte High Enable or Write High output as selected by the CCR BHE will go
low for external writes to the high byte of the data bus WRH will go low for
external writes where an odd byte is being written BHE WRH is activated
only during external memory writes
BUSWIDTH (P5 7)
Input for bus width selection If CCR bits 1 and 2 ^e 1 this pin dynamically
controls the bus width of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs If it is high a 16-bit cycle occurs This pin can be used as
standard I O when not used as BUSWIDTH
CAPCOMP0 – CAPCOMP5
(P2 0–P2 3 P7 0–P7 1)
The EPA Capture Compare pins CAPCOMP0 – 3 share the pins with
P2 0–P2 3 CAPCOMP4 – 5 share the pins with P7 0 – P7 1 If not used for the
EPA they can be configured as standard I O pins
CLKOUT
Output of the internal clock generator The frequency is of the oscillator
frequency It has a 50% duty cycle
COMPARE0 – COMPARE5
(P2 4–P2 7 P7 2–P7 3)
The EPA Compare pins COMPARE0 – 3 share the pins with P2 4 – P2 7
COMPARE4–5 share the pins with P7 2 – P7 3 If not used for the EPA they
can be configured as standard I O pins
EA
External Access enable pin EA ^e 0 causes all memory accesses to be
external to the chip EA ^e 1 causes memory accesses from location 2000H
to 5FFFH to be from the on-chip OTPROM ROM EA ^e 12 5V causes
execution to begin in the programming mode EA is latched at reset
EXTINT
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH The input may be selected to be a
positive negative edge or a high low level using WG PROTECT (1FCEH)
FREQOUT
Programmable frequency output pin The frequency can vary from 4 KHz to 1
MHz (16 MHz input clock) It has a 50% duty cycle Pin may be configured as
standard I O if FREQOUT is not used
INST (P5 1)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle It is low otherwise This pin can be configured as
standard I O if not used as INST
NMI
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH If not used it should be tied to V_SS May
be used by Intel Evaluation boards
PORT0
8-bit high impedance input-only port Also used as A D converter inputs
Port0 pins should not be left floating These pins also used to select
programming modes in the OTPROM devices
PORT1
8-bit high impedance input-only port P1 0 – P1 5 are also used as A D
converter inputs In addition P1 2 and P1 3 can be used as Timer 1 clock
input and direction select respectively P1 6 – P1 7 can be used as input-only
pins
9