80C51FA Datasheet, PDF (8/13 Pages) Intel Corporation – EVENT-CONTROL CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

AUTOMOTIVE 80C51FA 83C51FA
DC CHARACTERISTICS (T_A ^{e b}40 C to ^a125 C V_CC ^e 5V g10% V_SS ^e 0V) (Continued)
Symbol
Parameter
Min Typ
Max Unit Test Conditions
I_TL
Logical 1 to 0 Transition Current
(Ports 1 2 and 3)
b₂₆₅ b_{650 mA VIN} e _2V
RRST
RST Pulldown Resistor
40
100
225
KX
CIO
Pin Capacitance
10
pF
1MHz 25 C
I_CC
Power Supply Current
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode (I_PD)
(Note 3)
40
mA
15
mA
150
mA
NOTES
1 Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V_OLs of ALE and Ports 1 and 3
The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operations In applications where capacitance loading exceeds 100 pFs the noise pulse on the ALE
signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch
with a Schmitt Trigger Strobe input
2 Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the 0 9 V_CC specification when the
address lines are stabilizing
3 See Figures 6 – 9 for test conditions Minimum V_CC for Power Down is 2 0V
4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and
5 0V
5 Under steady state (non-transient) conditions I_OL must be externally limited as follows
Maximum I_OL per Port Pin
10 mA
Maximum I_OL per 8-Bit Port -
Port 0
26 mA
Ports 1 2 and 3
15 mA
Maximum Total I_OL for all Output Pins
71 mA
If I_OL exceeds the test condition V_OL may exceed the related specification Pins are not guaranteed to sink current greater
than the listed test conditions
6 Contact Intel for design-in information
8