LXT9762 Datasheet, PDF (68/78 Pages) Intel Corporation – Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII

LXT9762/9782 — Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII
Table 41. PHY Identification Register 2 (Address 3)
Bit
Name
Description
3.15:10
PHY ID number
The PHY identifier composed of bits 19 through 24 of
the OUI.
3.9:4
Manufacturer’s
model number
6 bits containing manufacturer’s part number.
3.3:0
Manufacturer’s
revision number
4 bits containing manufacturer’s revision number.
1. RO = Read Only
Type ¹
RO
RO
RO
Default
011110
001000 (LXT9762)
001011 (LXT9782)
XXXX
Figure 41. PHY Identifier Bit Mapping
abc
rs
x
Organizationally Unique Identifier
123
18 19
24
0
0
1
3
I/G
15
0 15
10 9
43
0
PHY ID Register #1 (Address 2)
PHY ID Register #2 (Address 3)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0XXXXXXXXXX
0
0
0
2
00
20
The Level One OUI is 00207B hex.
B
7
7B
5
03
0
Manufacturer’s
Model Number
Revision
Number
Table 42. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type ¹
4.15
Next Page
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
R/W
4.14
Reserved
Ignore.
RO
4.13
Remote Fault
1 = Remote fault.
0 = No remote fault.
R/W
4.12
Reserved
Ignore.
R/W
4.11
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
R/W
4.10 Pause
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
R/W
1. R/W = Read/Write
RO = Read Only
LHR = Latches High on Reset
2. The default setting of bit 4.10 (PAUSE) is determined by pin 79.
3. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to Reset discussion on page 27.
Default
1
0
0
0
0
Note 2
68
Datasheet