273943-004US Datasheet, PDF (61/68 Pages) Intel Corporation – Intel 80331 I/O Processor

Intel® 80331 I/O Processor Datasheet
Electrical Specifications
4.4.4
Table 29.
4.4.5
I²C Interface Signal Timings
I²C Signal Timings
Symbol
Parameter
Std. Mode
Min. Max
Fast Mode
Min. Max
Units Notes
F_SCL SCL Clock Frequency
0 100
0
400
T_BUF Bus Free Time Between STOP and START 4.7
1.3
Condition
T_HDSTA Hold Time (repeated) START Condition
4
0.6
T_LOW SCL Clock Low Time
4.7
1.3
T_HIGH SCL Clock High Time
4
0.6
T_SUSTA Setup Time for a Repeated START Condition 4.7
0.6
T_HDDAT Data Hold Time
0 3.45
0
0.9
T_SUDAT Data Setup Time
250
100
T_SR SCL and SDA Rise Time
1000 20+0.1C_b 300
T_SF SCL and SDA Fall Time
300 20+0.1C_b 300
T_SUSTO Setup Time for STOP Condition
4
0.6
NOTES:
1. See Figure 9 “I2C/SMBus Interface Signal Timings” on page 64.
2. Not tested.
3. After this period, the first clock pulse is generated.
4. C_b = the total capacitance of one bus line, in pF.I²C
KHz
µs (1)
µs (1, 3)
µs (1, 2)
µs (1, 2)
µs (1)
µs (1)
ns (1)
ns (1, 4)
ns (1, 4)
µs (1)
UART Interface Signal Timings
Table 30. UART Signal Timings
Symbol
Parameter
T_XD1 Ux_TXD output delay from M_CK rising edge
T_RXS1 Ux_RXD data setup time (to M_CK rising edge).
T_RXH1 Ux_RXD data hold time (to M_CK rising edge).
T_CTS1 Ux_CTS setup time (to M_CK rising edge).
T_CTH1 Ux_CTS hold time (to M_CK rising edge).
T_RTS1 Ux_RTS setup time (to M_CK rising edge).
T_RTH1 Ux_RTS hold time (to M_CK rising edge).
1. See Figure 10 “UART Transmitter Receiver Timing” on page 64.
Std. Mode
Min.
50
50
60
60
60
60
Max
60
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1
Document Number: 273943-004US
August 2005
61