319282-007 Datasheet, PDF (552/586 Pages) Intel Corporation – 10 GbE Controller

Intel^® 82598 10 GbE Controller
The frequency tolerance for the PCIe reference clock is +/- 300 ppm.
8.1.4 Bias Resistor
For proper biasing of the PCIe analog interface, a 1.40 K 1% resistor needs to be connected between
the PE_RCOMP_P and PE_RCOMP_N pins. To avoid noise coupled onto this reference signal, place the
bias resistor close to the controller chip and keep traces as short as possible.
8.1.5 Miscellaneous PCIe Signals
The Ethernet controller signals power management events to the system by pulling low the PE_WAKE#
signal. This signal operates like the familiar PCI PME# signal. Somewhere in the system, this signal has
to be pulled high to the auxiliary 3.3 V dc supply rail.
The PE_RST# signal, which serves as the familiar reset function for the controller, needs to be
connected to the host system’s corresponding signal.
8.2
Connecting the MAUI Interfaces
The controller has two High Speed Network Interfaces which can be configured in different 1 and
10 Gb/s operation modes: BX, CX4, KX, KX4, XAUI. Choose the appropriate configuration for your
environment.
8.3
MAUI Channels Lane Connections
For BX and KX connections, only the first lane has to be connected (TXx_L0_P, TXx_L0_N; RXx_L0_P,
RXx_L0_N). For the rest of the interfaces, all four differential pairs have to be connected per each
direction.
These signals are 100  terminated differential signals that are AC coupled near the receiver. Place the
AC coupling caps less than 1 inch away from the receiver. For recommended capacitor values, consult
the IEEE 802.3 specifications. Capacitor size should be small to reduce parasitic inductance. Use X5R or
X7R, +10% capacitors in a 0402 or 0201 package size.
8.3.1 Bias Resistor
For proper biasing of the MAUI analog interface a 6.49 K 1% resistor needs to be connected between
the RBIAS and ground. To avoid noise coupled onto this reference signal, place the bias resistor close to
the controller chip and keep traces as short as possible.
8.3.2 XAUI, KX/KX4, CX4 and BX Layout Recommendations
This section provides recommendations for routing high-speed interface. The intent is to route this
interface optimally using FR4 technology. Intel has tested and characterized these recommendations.
8.3.2.1 Board Stack Up Example
Printed circuit boards for these designs typically have six, eight, or more layers. Although, the 82598
does not dictate stackup, the following examples are of typical stackups.
Intel^® 82598 10 GbE Controller
Datasheet
552
Reference Number: 319282-007
Revision Number: 3.2
October 2010