273804-002 Datasheet, PDF (33/82 Pages) Intel Corporation – Ultra-Low Voltage Intel-R Celeron-R Processor (0.13 u in the Micro FC-BGA Package

Ultra-Low Voltage Intel^® Celeron^® Processor — 650 MHz and 400 MHz
Table 20. AGTL Bus DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
V_CCT
V_REF
Bus Termination Voltage
Input Reference Voltage
1.25
V
2_{/3VCCT – 2%}
2_/3VCCT
2_{/3VCCT + 2%}
V
1
±2%, 2
R_TT Bus Termination Strength
50
56
65
W
On-die R_TT, 3
NOTES:
1. Refer to Table 14 for minimum and maximum values.
2. V_REF should be created from V_CCT by a voltage divider.
3. The RESET# signal does not have an on-die R_TT. It requires an off-die 56.2 Ω ±1% terminating resistor connected to V_CCT.
Table 21. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
(Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
V_IL15
Input Low Voltage, 1.5 V
CMOS
–0.15
V_CMOSREFmin – 300 mV
V
V_IL18
Input Low Voltage, 1.8 V
CMOS
–0.36
0.36
V
1, 2
V_IH15
Input High Voltage, 1.5 V
CMOS
V_CMOSREFmax + 250 mV
2.0
V
10
V_IH15PICD
Input High Voltage, 1.5 V
PICD[1:0]
V_CMOSREFmax + 200 mV
2.0
V
11
V_IH18
Input High Voltage, 1.8 V
CMOS
1.44
2.0
V
1, 2
V_OH15
Output High Voltage, 1.5 V
CMOS
N/A
1.615
All outputs
V
are
Open-drain
V_OH33
Output High Voltage, 3.3 V
signals
2.0
3.465
V
3.3V + 5%
V_OL33
Output Low Voltage, 3.3 V
signals
0.8
V
V_OL
Output Low Voltage
0.3
V
8
V_CMOSREF CMOSREF Voltage
0.90
1.10
V
4
V_CLKREF CLKREF Voltage
1.187
1.312
V
9
NOTES:
1. Parameter applies to the PWRGOOD signal only.
2. V_Ilx,min and V_Ihx,max only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the low state.
See Tables 28 and 29 for DC levels when BCLK and BCLK# are stopped.
3. Measured at 9 mA.
4. V_CMOSREF should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply to maintain
noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that drive these signals.
5. (0 ≤ _VIN/OUT ≤ V_Ihx,max).
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, V_OL,max cannot be ensured
if this specification is exceeded.
7. Parameter applies to VTTPWRGD signal only.
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC Tolerance must
be less than –40 dB @ 1 MHz.
10.Applies to all TAP and CMOS signals (not to APIC signals).
11. Applies to PICD[1:0].
Datasheet
33