326769-002 Datasheet, PDF (306/342 Pages) Intel Corporation – Mobile 3rd Generation Intel® Core™ Processor Family

Processor Configuration Registers
2.19.11 SSKPD—Sticky Scratchpad Data Register
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
0/0/0/MCHBAR PCU
5D10–5D17h
0000000000000000h
RWS, RW
64 bits
Bit
63:32
31:30
29:24
23
22
21:16
15:14
Access
Reset
Value
RST/
PWR
Description
RWS
RWS
RWS
00000000h
00b
00h
Powergood
Powergood
Powergood
Scratchpad Data (SKPD)
2 WORDs of data storage.
Reserved for Future Use (RWSVD3)
Bit 30 controls the way BIOS calculate WM3 value.
Bit 31 is reserved for future use.
DDRIO Power down Shutdown Latency Time (WM3)
Number of microseconds to access memory if memory is in
Self Refresh (SR) with
DDRIO in Power down (EPG mode) (0.5 us granularity).
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
RWS
RW
RWS
0b
0b
000000b
Powergood
Uncore
Powergood
Note:
The value in this field corresponds to the memory
latency requested to the Display Engine when Memory
PLL Shutdown is enabled. The Display LP3 latency and
watermark values (GTTMMADR offset 45110h) should
be programmed to match the latency in this register.
Reserved for Future Use (RWSVD2)
Reserved for Future Use
MPLL Fast Lock Disable (MPLL_FAST_DIS)
Copy of CR PCU [SBPLL_FAST_DIS]
MPLL Shutdown Latency Time (WM2)
Number of microseconds to access memory if the MPLL is
shutdown (requires memory in Self Refresh). The value is
programmed in 0.5 us granularity.
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
RWS
Note:
The value in this field corresponds to the memory
latency requested to the Display Engine when MPLL
shutdown is enabled. The Display LP2 latency and
watermark values (GTTMMADR offset 4510Ch) should
be programmed to match the latency in this register.
00b
Powergood
Reserved for Future Use (RWSVD1)
Reserved for Future Use
306
Datasheet, Volume 2