I211-AT Datasheet, PDF (3/5 Pages) Intel Corporation – Low-power, small-footprint, single-port gigabit network connectivity with advanced performance features.

External Interfaces
PCI Express* Interface v2.1
Network Interfaces
BOM Cost Reduction
Feature
On-chip integrated Switching Voltage Regulator
(iSVR)
• 2.5 GT/s Support for x1 width (Lane)
• MDI (Copper) standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T ap-
plications (802.3, 802.3u, and 802.3ab)
Benefits
• Removes need for a higher cost on-board voltage regulator
Ethernet Features
IEEE* 802.3* auto-negotiaton
1 Gb/s Ethernet IEEE 802.3, 802.3u, 802.3ab PHY
specifications compliant
Integrated PHY for 10/100/1000 Mb/s for multi-
speed, full, and half-duplex
IEEE 802.3x and IEEE 802.3z compliant flow control
support with software-controllable Rx thresholds
and Tx pause frames
Automatic cross-over detection function (MDI/
MDI-X)
IEEE 1588 protocol and 802.1AS implementation
• Automatic link configuration for speed duplex and flow control
• Robust operation over installed base of Cat5 twisted-pair cabling
• Smaller footprint and lower power dissipation compared to multiple discreet MAC and PHYs
• Local control of network congestion levels
• Frame loss reduced from receive overruns
• The PHY automatically detects which application is being used and configures itself accordingly
• Time-stamping and synchronization of time sensitive applications
• Distribute common time to media devices
Power Management and Efficiency
<730 mW S0-Max (state) 1000BASE-T Active 70 ^oC
IEEE 802.3az - Energy Efficient Ethernet (EEE)
Smart Power Down (SPD) at S0 no link/Sx no link
Active State Power Management (ASPM)
LAN disable function
• Controller is designed for low power consumption
• Power consumption by the PHY is reduced by approximately 50%; link transitions to low power Idle (LPI)
state as defined in the IEEE 802.3az (EEE) standard
• PHY powers down circuits and clocks that are not required for detection of link activity
• Optionality Compliance bit enables ASPM or runs ASPM compliance tests to support entry to L0s
• Option to disable the LAN Port and/or PCIe Function.
Full wake up support:
• Advanced Power Management (APM) Support–
[formerly Wake on LAN]
• Advanced Configuration and Power Interface
(ACPI) specification v2.0c
• Magic Packet* wake-up enable with unique MAC
address
• APM - Designed to receive a broadcast or unicast packet with an explicit data pattern (Magic Pack) and
assert a signal to wake up the system
• ACPI - PCIe power management based wake-up that can generate system wake-up events from a num-
ber of sources
ACPI register set and power down functionality sup- • Power-managed speed control lowers link speed/power when highest link performance is not required
porting D0 and D3 states
MAC Power Management controls
• Power management controls in the MAC /PHY enable the device to enter a low-power state
Low Power Link Up - Link Speed Control
• Enables a link to come up at the lowest possible speed in cases where power is more important than
performance
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