82574L Datasheet, PDF (3/4 Pages) Intel Corporation – Low-Power, Small-Footprint, Single-Port Gigabit Network Connectivity with Advanced Performance Features

Features
Benefits
Gigabit MAC/PHY Performance Features
Integrated PHY for 10/100/1000 Mb/s for multi-speed, full, and
half-duplex operation
Two optimized transmit (Tx) and receive (Rx) queues for
the Controller’s single port
Descriptor ring management hardware for Transmit and Receive
Legacy and Message Signal Interrupt (MSI) Modes
Message Signal Interrupt Extension (MSI-X)
Receive Side Scaling (RSS) for Windows* environment and
Scalable I/O for Linux* environments (IPv4, IPv6, TCP/UDP)
64-bit address master support for systems using more
than 4 GB of physical memory
Programmable host memory receive buffer per queue
(256 Bytes to 16 KBytes) and cache line size (64 Bytes
to 128 Bytes)
40 KB Packet buffer size; Configurable Rx and Tx data FIFO
programmable in 1 KB increments
Support for transmission and reception of packets up to
9018 Bytes (Jumbo Frames)
Compliant with 1 Gb/s Ethernet IEEE 802.3, 802.3u, 802.3ab PHY specifications
IEEE 802.3x and 802.3z compliant flow control support with software-
controllable Rx thresholds and Tx pause frames
• Smaller footprint and lower power dissipation compared to multiple discreet
MAC and PHY solutions
• Efficient packet prioritization
• Network packet handling without waiting or buffer overflow
• Optimized descriptor fetch and write-back mechanisms for efficient system
memory and PCIe bandwidth usage
• Interrupt mapping
• Advanced interrupt mapping for load balancing across multiple cores
• More vectors per function
• Software-controlled aliasing when fewer vectors are allocated than requested,
and ability for each vector to use independent address and data value
• Two receive queues to enable traffic streams to be distributed into queues and
directed to specific CPU cores
• Efficient use of PCIe bus and system memory
• Efficient use of PCIe bus and system memory
• FIFO size adjustable to the application
• Enables higher and better throughput of data
• Robust operation over installed base of Category-5 twisted-pair cabling
• Local control of network congestion levels
• Reduce receive buffer overflows
• Frame loss reduced from receive overruns
Host Offloading Features
TCP/UDP, IPv4, and IPv6 checksum offloads; Extended Tx descriptors
for more offload capabilities
TCP Segmentation/Transmit Segmentation Offloading (TSO)
IEEE 802.1q Virtual Local Area Network (VLAN) support with VLAN tag
insertion, stripping and packet filtering for up to 4096 VLAN tags
IEEE 802.1q advanced packet filtering
Header/packet data split in receive
• Improved CPU utilization
• Improved CPU utilization
• Adding (for transmits) and ping (for receives) of VLAN tags
• Filtering packets belonging to certain VLANs
• 16 exact-matched packets (unicast or multicast)
• 4096-bit hash filter for multicast frames
• Lower processor utilization
• Promiscuous (unicast and multicast) transfer mode support
• Optional filtering of invalid frames
• Helps the driver to focus on the relevant part of the packet without the
need to parse it
Manageability Features
DMTF Network Controller Sideband Interface (NC-SI)
SMBus pass through
Preboot eXecution Environment (PXE) flash interface support
iSCSI boot
Management Data Input/Output (MDIO) – internal management interface
MAC/PHY Control and Status
Watchdog timer
• Supports pass-through traffic between BMC and Controller’s LAN functions
• Supports configuration traffic between the BMC and the Controller’s internal units
• Allows fast data rate (up to 100 Mb/s full duplex)
• Allows for advanced BMC capabilities such as video redirection
• Enables system-level component connections for manageability purposes
• Enables BMC to configure the Controller’s filters and management-related capabilities
• Data rates up to 400 KHz
• Enables system boot up via the EFI (32-bit and 64-bit)
• Flash interface for PXE 2.1 option ROM
• Enables system boot up via iSCSI
• Provides additional network management capability
• Enables the MAC and software to monitor and control the state of the PHY
• Enhanced control capabilities through PHY reset, PHY link status, PHY duplex
indication, and MAC Dx power state indication
• Defined by the FLASHT register to minimize Flash updates