82572EI Datasheet, PDF (3/4 Pages) Intel Corporation – High-performance Gigabit Network Connectivity for Servers and Embedded System Designs

Additional Device Features
Integrated SerDes
Four outputs that directly drive LEDs with programmable LED functionality
Internal phase-locked loop (PLL) for clock generation can use 25-MHz crystal
JTAG (IEEE 1149.1*) test access port built-in silicon
Loop-back capability
Characteristics
Electrical
PCI Express signaling
Typical targeted power dissipation (in active link state)
Environmental
Operating temperature
Storage temperature
Physical
Implemented in 90nm complementary metal-oxide semiconductor
(CMOS) process
Package
• Supports backplane and fiber optic applications
• Software-definable function (speed, link, activity) and blinking allow flexible LED signaling implementations
• Lower component count and reduced system cost
• Simplified testing using boundary scan
• Built-in tests for silicon integrity
• 3.3 V
• 1.4 W @ D0 1000 Mbps
• 370 mW @ D3 100 Mbps (wakeup enabled)
• 175 mW @ D3 wakeup disabled
• 0° to 70° C
• – 65° C to 140° C
• Offers lowest geometry to minimize power and size while maintaining quality and reliability
• Lead-free¹ 256-pin Flip-Chip Ball Grid Array (FC-BGA) package
High-Performance Design Features
The Intel 82572EI Gigabit Ethernet Controller for PCI Express
is designed for high performance and low memory latency.
The device is optimized to connect to a system Memory Control
Hub (MCH) using up to four PCI Express lanes. Alternatively,
the controller can connect to an Input/Output (I/O) Control Hub
(ICH) that has a PCI Express interface. Wide internal data paths
eliminate performance bottlenecks by efficiently handling large
address and data words. Combining a parallel and pipelined
logic architecture that is optimized for Gigabit Ethernet and for
independent transmit and receive queues, the controller efficiently
handles packets with minimum latency. The controller includes
advanced interrupt-handling features and uses efficient ring-buffer
descriptor data structures, with up to 64 packet descriptors
cached on chip. A large 48 KByte per port on-chip packet buffer
maintains superior performance. In addition, using hardware
acceleration, the controller offloads tasks from the host, such
as checksum calculations for transmission control protocol (TCP),
user datagram protocol (UDP), and Internet protocol (IP); header
and data splitting; and TCP segmentation.
The Intel 82572EI Gigabit Ethernet Controller package is a
17 mm x 17 mm, 256-ball grid array.
Order Codes
82572EI
82572EI lead-free¹
• HL82572EI
• JL82572EI