EE80C188XL20 Datasheet, PDF (29/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
AC SPECIFICATIONS (Continued)
CLOCK TIMINGS
T_A ^e 0 C to ^a70 C V_CC ^e 5V g10%
All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted
All output test conditions are with C_L ^e 50 pF
For AC tests input V_IL ^e 0 45V and V_IH ^e 2 4V except at X1 where V_IH ^e V_CC ^b 0 5V
Values
Symbol Parameter
80C186XL25
80C186XL20
80C186XL12 Unit
Min
Max
Min
Max
Min
Max
Test
Conditions
80C186XL CLKIN REQUIREMENTS⁽¹⁾
T_CKIN CLKIN Period
20
%
25
%
40
% _ns
T_CLCK CLKIN Low Time
8
%
10
%
16
% _{ns 1 5V}(2)
T_CHCK CLKIN High Time
8
%
10
%
16
% _{ns 1 5V}(2)
T_CKHL CLKIN Fall Time
5
5
5 ns 3 5 to 1 0V
T_CKLH CLKIN Rise Time
5
5
5 ns 1 0 to 3 5V
80C186XL CLKOUT TIMING
T_CICO CLKIN to
CLKOUT Skew
17
17
21 ns
T_CLCL
T_CLCH
CLKOUT Period
40
%
50
CLKOUT
Low Time
0 5 T_CLCL ^b 5
0 5 T_CLCL ^b 5
80
% _ns
0 5 T_CLCL ^b 5
ns C_L ^e 100 pF⁽³⁾
T_CHCL CLKOUT
High Time
0 5 T_CLCL ^b 5
0 5 T_CLCL ^b 5
0 5 T_CLCL ^b 5
ns C_L ^e 100 pF⁽⁴⁾
T_CH1CH2 CLKOUT
Rise Time
6
8
10 ns 1 0 to 3 5V
T_CL2CL1 CLKOUT
Fall Time
6
8
10 ns 3 5 to 1 0V
NOTES
1 External clock applied to X1 and X2 not connected
2 T_CLCK and T_CHCK (CLKIN Low and High times) should not have a duration less than 40% of T_CKIN
3 Tested under worst case conditions V_CC e 5 5V T_A e 70 C
4 Tested under worst case conditions V_CC e 4 5V T_A e 0 C
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