LXP730 Datasheet, PDF (28/70 Pages) Intel Corporation – Multi-Rate DSL Framer

LXP730 — Multi-Rate DSL Framer
3.0
Application Information
3.1
Typical Applications
This section shows some block diagrams to serve as example applications. Connections to the
LXP730 as shown emphasize those relevant for the application. Detailed connections to the
processor are not shown.
Figure 6 demonstrates how the LXP730 can simultaneously handle voice from a PCM circuit and
packet-type data from an HDLC style device.
Figure 7 is an example of the HWC mode. The codecs’ digital interfaces connect directly to the
LXP730. An external device is needed to handle signalling information for each voice line
supported. In this case the Z bits could be used to carry the signalling information such as off-hook
status from the CPE and ringing signal from the CO. An FPGA or a fast dedicated processor could
handle these tasks.
Figure 6. High Performance Voice/Data Transport
2.048/4.096 Mbps
PCM Highway
PDI
PDO
PCLK
PFRM
HDLC
4
PCM
LXP730
Framer
ADPI
TDATA
RDATA
QUATCLK
BIT_CK
SK70725/21
Data Pump
µP - Router
Nx64 kbps
Channels
Packet/Cell
Data
LAN
Transceiver
LXT905
Microprocessor Bus
28
Datasheet