28F200BL-TB Datasheet, PDF (28/42 Pages) Intel Corporation – 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

28F200BL-T B 28F002BL-T B
continue to perform the erase or program function
and consume program or erase active power until
program or erase is completed
4 5 4 RESET DEEP POWER-DOWN
The 2-Mbit flash family supports a typical I_CC of
0 2 mA in deep power-down mode One of the target
markets for these devices is in portable equipment
where the power consumption of the machine is of
prime importance The 2-Mbit flash family has a
RP pin which places the device in the deep power-
down mode When RP is at a logic-low (GND
g0 2V) all circuits are turned off and the device typ-
ically draws 0 2 mA of V_CC current
During read modes the RP pin going low dese-
lects the memory and places the output drivers in a
high impedance state Recovery from the deep pow-
er-down state requires a maximum of 600 ns to ac-
cess valid data (t_PHQV)
During erase or program modes RP low will abort
either erase or program operation The contents of
the memory are no longer valid as the data has been
corrupted by the RP function As in the read mode
above all internal circuitry is turned off to achieve
the 0 2 mA current level
RP transitions to V_IL or turning power off to the
device will clear the status register
The use of RP during system reset is important
with automated write erase devices When the sys-
tem comes out of reset it expects to read from the
flash memory Automated flash memories provide
status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel’s
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of RP input
In this application RP is controlled by the same
RESET signal that resets the system CPU
4 6 Power-Up Operation
The 2-Mbit flash family is designed to offer protec-
tion against accidental block erasure or program-
ming during power transitions Upon power-up the
2-Mbit flash family is indifferent as to which power
supply V_PP or V_CC powers-up first Power supply
sequencing is not required
The 2-Mbit flash family ensures the CUI is reset to
the read mode on power-up
In addition on power-up the user must either drop
CE low or present a new address to ensure valid
data at the outputs
28
A system designer must guard against spurious
writes for V_CC voltages above V_LKO when V_PP is
active Since both WE and CE must be low for a
command write driving either signal to V_IH will inhibit
writes to the device The CUI architecture provides
an added level of protection since alteration of mem-
ory contents can only occur after successful com-
pletion of the two-step command sequences Finally
the device is disabled until RP is brought to V_IH
regardless of the state of its control inputs This fea-
ture provides yet another level of memory protec-
tion
4 7 Power Supply Decoupling
Flash memory’s power switching characteristics re-
quire careful device decoupling methods System
designers are interested in 3 supply current issues
 Standby current levels (I_CCS)
 Active current levels (I_CCR)
 Transient peaks produced by falling and rising
edges of CE
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks Each
flash device should have a 0 1 mF ceramic capacitor
connected between each V_CC and GND and be-
tween its V_PP and GND These high frequency low-
inherent inductance capacitors should be placed as
close as possible to the package leads
4 7 1 V_PP TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system requires special consideration of the
V_PP power supply trace by the printed circuit board
designer The V_PP pin supplies the flash memory
cell’s current for programming and erasing One
should use similar trace widths and layout consider-
ations given to the V_CC power supply trace Ade-
quate V_PP supply traces and decoupling will de-
crease spikes and overshoots
4 7 2 V_CC V_PP AND RP TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by V_PP or CE tran-
sitions or WSM actions Its state upon power-up af-
ter exit from deep power-down mode or after V_CC
transitions below V_LKO (Lockout voltage) is Read
Array mode
After any word byte write or block erase operation is
complete and even after V_PP transitions down to
V_PPL the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired