RC28F128J3A_13 Datasheet, PDF (23/72 Pages) Intel Corporation – Intel StrataFlash® Memory

28F256J3, 28F128J3, 28F640J3, 28F320J3
Table 8. Read Operations (Sheet 2 of 2)
Asynchronous
Specifications
(All units in ns unless
otherwise noted)
Speed
Bin
-110
VV_CCCCQ^{==22.7.7VV––33.6.6VV(3(3))}
-115
-120
-125
-150
Notes
# Sym Parameter Density Min Max Min Max Min Max Min Max Min Max
R12
t_FLQV/
t_FHQV
BYTE# to Output Delay
1000
1000
1000
R13 t_FLQZ BYTE# to Output in High Z
1000
1000
1000
R14 t_EHEL CEx High to CEx Low
0
0
0
R15 t_APA Page Address Access Time
25
25
25
R16 t_GLQV OE# to Array Output Delay
25
25
25
NOTES:
CE_X low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE_X high is
defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew
rate.
2. OE# may be delayed up to t_ELQV-t_GLQV after the first edge of CE0, CE1, or CE2 that
enables the device (see Table 13) without impact on t_ELQV.
3. See Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6
V” on page 29 and Figure 16, “Transient Equivalent Testing Load Circuit” on
page 30 for testing characteristics.
4. When reading the flash array a faster t_GLQV (R16) applies. Non-array reads refer to
Status Register reads, query reads, or device identifier reads.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (t_APA) will equal R2
(t_AVQV).
1000
1000
1000
1000
0
0
30
25
25
25
1,2
1,2,5
1,2,5
5, 6
4
Figure 9. Single Word Asynchronous Read Waveform
Address [A]
CEx [E]
OE# [G]
WE# [W]
Data [D/Q]
BYT E# [F]
RP# [P]
R2
R3
R7
R6
R11
R4
R16
R12
R5
R1
R13
R8
R9
R10
Datasheet
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