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INTEL82801 Datasheet, PDF (195/414 Pages) Intel Corporation – 82801AB (ICH0) I/O Controller Hub | |||
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LPC Interface Bridge Registers (D31:F0)
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
RIDâRevision ID Register (LPC I/FâD31:F0)
Offset Address: 08h
Default Value: See ICH Spec. Updates
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification Number. 8-bit value that indicates the revision number for the LPC bridge.
Refer to ICH Specification Updates for this value.
PIâProgramming Interface (LPC I/FâD31:F0)
Address Offset: 09h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
7:0 Programming Interface Value.
Description
SCCâSub-Class Code Register (LPC I/FâD31:F0)
Offset Address: 0Ah
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Sub-Class Code. 8-bit value that indicates the category of bridge for the LPC PCI bridge.
BCCâBase-Class Code Register (LPC I/FâD31:F0)
Offset Address: 0Bh
Default Value: 06h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Base Class Code. 8-bit value that indicates the type of device for the LPC bridge. The code is 06h
indicating a bridge device.
HEADTYPâHeader Type Register (LPC I/FâD31:F0)
Offset Address: 0Eh
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-function Device. This bit is â1â to indicate a multi-function device.
6:0 Header Type. 8-bit field identifies the header layout of the configuration space.
82801AA and 82801AB Datasheet
8-5
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