AS87C196CB20F8 Datasheet, PDF (19/38 Pages) Intel Corporation – 16-Bit CHMOS Microcontrollers

Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers
Table 6. AC Characteristics (Sheet 2 of 2)
(over specified operating conditions); Test conditions: capacitance load on all
pins = 100 pF, Rise and fall times = 10 ns, F_OSC = 16 MHz
Symbol
Parameter
Min
Max
Units
T_LLRL
ALE/ADV# Falling Edge to RD# Falling Edge
T_OSC – 30
ns
T_RLCL RD# Low to CLKOUT Falling Edge
4
30
ns
T_RLRH
T_RHLH
T_RLAZ
RD# Low Period
RD# Rising Edge to ALE/ADV# Rising Edge
RD# Low to Address Float
T_OSC – 5
CA: T_OSC – 10
T_OSC
T_OSC + 25
5
ns
ns⁽⁴⁾
ns⁽⁶⁾
T_LLWL ALE/ADV# Falling Edge to WR# Falling Edge
T_OSC – 10
ns
T_CLWL CLKOUT Low to WR# Falling Edge
–5
25
ns
T_QVWH Data Stable to WR# Rising Edge
T_OSC – 23
ns
T_CHWH CLKOUT High to WR# Rising Edge
–10
15
ns
T_WLWH WR# Low Period
T_OSC – 20
ns
T_WHQX
T_WHLH
Data Hold after WR# Rising Edge
WR# Rising Edge to ALE/ADV# Rising Edge
T_OSC – 25
T_OSC – 10
T_OSC + 15
ns
ns⁽⁴⁾
T_WHBX
T_WHAX
BHE#, INST Hold after WR# Rising Edge
AD[15:8] Hold after WR# Rising Edge
T_OSC – 10
T_OSC – 30
ns
ns⁽⁵⁾
T_RHBX
T_RHAX
BHE#, INST Hold after RD# Rising Edge
AD[15:8] Hold after RD# Rising Edge
T_OSC – 10
T_OSC – 30
ns
ns⁽⁵⁾
NOTES:
1. If max is exceeded, additional wait states will occur.
2. Testing performed at 4 MHz; however, the device is static by design and will typically operate below 1 Hz.
3. Typical specifications, not guaranteed.
4. Assuming back-to-back bus cycles.
5. 8-bit bus only.
6. T_RLAZ (max) = 5 ns by design.
7. T_OFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure.
Datasheet
19