8051AH Datasheet, PDF (19/21 Pages) Intel Corporation – MCS51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS

MCS@51 CONTROLLER
PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against soft-
ware piracy.
ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 ad-
dress lines are used to select a byte of the Encryp-
tion Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the un-
programmed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Ar-
ray is used, at least one of the Lock Bits be pro-
grammed as well.
Table5. LockBitsandtheirFeatures
LB1
u
LogicEnabled
Minimum Program Lock features
enabled. (Code Verify WIIIstill be
=
P
u MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
I^P
P
Same as above, but Verify is also
disabled
I U
P IReservedfor Future Definition I
= Programmed
= Unprogrammed
LOCK BITS
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table
5.
Erasing the EPROM also erases the Encryption Ar-
ray and the Lock Bits, returning the part to full un-
locked functionality.
To ensure proper functionality of the chip, the inter-
nally latched value of the ~ pin must agree with its
external state.
READING THE SIGNATURE BYTES
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H) = 89H indicates manufactured by Intel
(031H) = 51H indicates 8751BH
52H indicates 8752BH
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