290688-001 Datasheet, PDF (165/172 Pages) Intel Corporation – Intel 815 Chipset Family 82815 Graphics and Memory Controller Hub (GMCH)

82815 GMCH
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6. Testability
In the GMCH, the testability for Automated Test Equipment (ATE) board level testing has been changed
from the traditional NAND chain mode to a XOR chain. The GMCH pins are grouped in eight XOR
chains.
An XOR-Tree is a chain of XOR gates each with one of its inputs connected to a GMCH input pin or bi-
directional pin (used as an input pin only). The other input of each XOR gate connects to the non-
inverted output of the previous XOR gate in the chain. The first XOR gate of each chain will have one
pin internally connected tied to Vcc. The output of the last XOR gate is the chain output. Figure 14
shows the GMCH XOR chain implementation.
Figure 14. XOR Tree Implementation
Vcc
Pin 1
Pin 2
Pin 3
Pin 4
XOR
Out
Pin 5
Pin 6
xor.vsd
Datasheet
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