8X930HX Datasheet, PDF (16/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS HUB PERIPHERAL CONTROLLER

8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER
4.0 SIGNALS
Signal
Name
A17
A16
A15:8
AD7:0
ALE
AV_CC
CEX2:0
CEX3
CEX4
D_M0, D_P0
D_M1, D_P1
D_M2, D_P2
D_M3, D_P3
D_M5, D_P5
Table 10. Signal Description (Sheet 1 of 4)
Type
O
O
O
I/O
O
PWR
I/O
I/O
I/O
Description
Address Line 17. Output to memory as 18th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
Address Line 16. Output to memory as 17th external address
bit in extended bus applications. Selected with bits RD1:0 in
configuration byte UCONFIG0. See Table 11 and RD#, WR#,
and PSEN#.
Address Lines. Upper address lines for external memory.
Description is for nonpage mode configuration. For page mode
configuration, data (D7:0) is multiplexed with the upper address
byte (A15:8).
Address/Data Lines. Multiplexed lower address lines and data
lines for external memory. Description is for nonpage mode
configuration. For page mode configuration, data (D7:0) is
multiplexed with the upper address byte (A15:8).
Address Latch Enable. ALE signals the start of an external
bus cycle and indicates that valid address information is
available on lines A15:8 and AD7:0. An external latch can use
ALE to demultiplex the address from the address/data bus.
Analog V_CC. A separate V_CC input for the phase-locked loop
circuitry.
Programmable Counter Array (PCA) Input/Output Pins.
These are input signals for the PCA capture mode and output
signals for the PCA compare mode and PCA PWM mode.
USB Port 0. D_P0 and D_M0 are the data plus and data minus
lines of USB port 0, the upstream differential port. These lines
do not have internal pullup resistors. Provide an external 1.5
KΩ pullup resistor at D_P0 to indicate the connection of a
fullspeed device.
NOTE: D_P0 low and D_M0 low signals an SE0 (USB reset),
causing the 8x930Hx to stay in reset.
USB Ports 1, 2, 3, and 5. D_P1, D_P2, D_P3, D_M1, D_M2, D_M3, D_M5,
and D_P5 are the data plus and data minus lines of USB ports 1,
2, 3, and 5, the four downstream differential ports. These lines
have no internal pulldown resistors. Provide an external 15 KΩ
pulldown resistor at each of these pins. (See “Unused
Downstream Ports” on page 33.)
Alternate
Function
P1.7/CEX4/WCLK
RD#
P2.7:0
P0.7:0
—
—
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
—
—
12
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