80C152JA Datasheet, PDF (16/17 Pages) Intel Corporation – UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER

8XC152JA JB JC JD
GSC TIMINGS (EXTERNAL CLOCK)
270431 – 17
NOTES
1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications
2 It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices
3 ‘‘Typicals’’ are based on samples taken from early manufacturing lots and are not guaranteed The measurements were
made with V_CC e 5V at room temperature
4 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations In the worst cases (capacitive loading ^l 100 pF) the noise pulse on the ALE pin may
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
5 Capacitive loading on Ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0 9V_CC specifi-
cation when the address bits are stabilizing
6 I_CC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns V_IL e V_SS a 0 5V V_IH e
V_CC b 0 5V XTAL2 N C Port 0 pins connected to V_CC ‘‘Operating’’ current is measured with EA connected to V_CC and
RST connected to V_SS ‘‘Idle’’ current is measured with EA connected to V_SS RST connected to V_CC and GSC inactive
7 The specifications relating to external data memory characteristics are also applicable to DMA operations
8 TQVWX should not be confused with TQVWX as specified for 80C51BH On 80C152 TQVWX is measured from data
valid to rising edge of WR On 80C51BH TQVWX is measured from data valid to falling edge of WR See timing diagrams
9 This value is based on the maximum allowable die temperature and the thermal resistance of the package
10 All specifications relating to external program memory characteristics are applicable to
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the 80C152JB JD
11 Same as TCLCH use External Clock Drive Waveform
12 Same as TCHCL use External Clock Drive Waveform
13 When using the same external clock to drive both the receiver and transmitter the minimum ECL spec effectively
becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) re-
quirements must also be met (150 a 45 e 195 ns) The 195 ns requirement would also increase to include the maximum
propagation delay between receivers and transmitters
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