28F004SC Datasheet, PDF (16/42 Pages) Intel Corporation – BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Table 4. Command Definitions⁽⁹⁾
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req’d. Notes Oper⁽¹⁾ Addr⁽²⁾ Data⁽³⁾ Oper⁽¹⁾ Addr⁽²⁾ Data⁽³⁾
Read Array/Reset
Read Identifier Codes
Read Status Register
1
Write X FFH
≥2
4
Write
X
90H Read
IA
ID
2
Write
X
70H Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5
Write BA 20H Write BA D0H
Program
2
5,6 Write PA 40H Write PA PD
or
10H
Block Erase and Program
Suspend
Block Erase and Program
Resume
1
5
Write
X
B0H
1
5
Write
X
D0H
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
2
7
Write BA 60H Write BA 01H
2
7
Write
X
60H Write
X
F1H
2
8
Write
X
60H Write
X
D0H
NOTES:
1. Bus operations are defined in Table 3.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 7 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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PRELIMINARY