M82380 Datasheet, PDF (14/134 Pages) Intel Corporation – HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

M82380
the single byte data on both halves of the bus When
the M80386 host processor reads from the M82380
the single byte data will be duplicated four times on
the Data Bus i e on D0–D7 D8–D15 D16– D23
and D24–D31
During Master Mode the M82380 can transfer 32-
16- and 8-bit data between memory (or I O devices)
and I O devices (or memory) via the Data Bus
2 2 3 ADDRESS BUS (A31–A2)
These three-state bidirectional signals are connect-
ed directly to the i386 Address Bus In the Slave
Mode they are used as input signals so that the
processor can address the M82380 internal ports
registers In the Master Mode they are used as out-
put signals by the M82380 to address memory and
peripheral devices The Address Bus is capable of
addressing 4 G-bytes of physical memory space
(00000000H to FFFFFFFFH) and 64 K-bytes of I O
addresses (00000000H to 0000FFFFH)
2 2 4 BYTE ENABLE (BE3 – BE0)
These bidirectional pins select specific byte(s) in the
double word addressed by A31 – A2 Similar to the
Address Bus function these signals are used as in-
puts to address internal M82380 registers during
Slave Mode operation During Master Mode opera-
tion they are used as outputs by the M82380 to ad-
dress memory and I O locations
In addition to the above function BE3 is used to
enable a production test mode and must be LOW
during reset The i386 processor will automatically
hold BE3 LOW during RESET
The definitions of the Byte Enable signals depend
upon whether the M82380 is in the Master or Slave
Mode These definitions are depicted in Table 1
Table 1 Byte Enable Signals
As INPUTS (Slave Mode)
BE3 –BE0
Implied A1 A0
Data Bits Written
to M82380
XXX0
00
XX01
01
X011
10
X111
11
D0 – D7
D8 – D15
D0 – D7
D8 – D15
X – DON’T CARE
During READ data will be duplicated on D0 –D7 D8 –D15 D16 – D23 and D24 – D31
During WRITE the M80386 host processor duplicates data on D0 – D15 and D16 – D31 so that the
M82380 is concerned only with the lower half of the Data Bus
As OUTPUTS (Master Mode)
BE3– BE0
Byte to be Accessed
Relative to A31–A2
Logical Byte Presented On
Data Bus During WRITE Only
D24–31 D16 –23 D8–15 D0 –7
1110
1101
1011
0111
1001
1100
0011
1000
0001
0000
0
1
2
3
12
01
23
012
123
0123
U
U
U
A
U
U
A
A
U
A
U
A
A
U
A
A
U
B
A
A
U
U
B
A
B
A
B
A
U
C
B
A
C
B
A
A
D
C
B
A
U e Undefined
A e Logical D0 – D7
B e Logical D8 – D15
C e Logical D16 – D23
D e Logical D24 – D31
Actual number of bytes accessed depends upon the programmed data path width
14