EN80C196NT Datasheet, PDF (11/31 Pages) Intel Corporation – CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE

8XC196NT
BUS MODE 0 and 3 AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions Capacitance Load on All Pins ^e 100 pF Rise and Fall Times ^e 10 ns
The 8XC196NT will meet these specifications
Symbol
F_XTAL
T_OSC
T_XHCH
T_OFD
T_CLCL
T_CHCL
T_CLLH
T_LLCH
T_LHLH
T_LHLL
T_AVLL
T_LLAX
T_LLRL
T_RLCL
T_RLRH
T_RHLH
T_RLAZ
T_LLWL
T_CLWL
T_QVWH
T_CHWH
T_WLWH
T_WHQX
T_WHLH
T_WHBX
T_WHAX
T_RHBX
T_RHAX
Parameter
Frequency on XTAL1
XTAL1 Period (1 F_XTAL)
XTAL1 High to CLKOUT High or Low
Clock Failure to Reset Pulled Low⁽⁶⁾
CLKOUT Period
CLKOUT High Period
CLKOUT Low to ALE ADV High
ALE ADV Low to CLKOUT High
ALE ADV Cycle Time
ALE ADV High Time
Address Valid to ALE Low
Address Hold After ALE ADV Low
ALE ADV Low to RD Low
RD Low to CLKOUT Low
RD Low Period
RD High to ALE ADV High
RD Low to Address Float
ALE ADV Low to WR Low
CLKOUT Low to WR Low
Data Valid before WR High
CLKOUT High to WR High
WR Low Period
Data Hold after WR High
WR High to ALE ADV High
BHE INST Hold after WR High
AD8–15 Hold after WR High
BHE INST Hold after RD High
AD8–15 Hold after RD High
Min
Max
40
20
50
250
a₂₀
110
4
40
2 T_OSC
T_OSC ^b 10
T_OSC ^a 30
b₁₀
a₁₅
b₂₅
a₁₅
4 T_OSC
T_OSC ^b 10
T_OSC ^a 10
T_OSC ^b 15
T_OSC ^b 40
T_OSC ^b 40
b₅
a₃₅
T_OSC ^b 5
T_OSC
T_OSC ^a 25
a₅
T_OSC ^b 10
b₁₀
a₂₅
T_OSC ^b 23
b₁₀
a₁₅
T_OSC ^b 30
T_OSC ^b 35
T_OSC ^b 10
T_OSC ^b 10
T_OSC ^b 30
T_OSC ^b 10
T_OSC ^b 30
T_OSC ^a 15
Units
MHz⁽¹⁾
ns
ns
ms
ns
ns
ns
ns
ns⁽⁵⁾
ns
ns
ns
ns
ns
ns⁽⁵⁾
ns⁽³⁾
ns
ns
ns
ns
ns
ns⁽⁵⁾
ns
ns⁽³⁾
ns
ns⁽⁴⁾
ns
ns⁽⁴⁾
NOTES
1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz
2 Typical specifications not guaranteed
3 Assuming back-to-back bus cycles
4 8-bit bus only
5 If wait states are used add 2 T_OSC c n where n e number of wait states If mode 0 (1 automatic wait state added)
operation is selected add 2 T_OSC to specification
6 T_OFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H NT NQ customer QROM codes need to equate location
2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired Intel manufacturing uses location 2016H
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit Programming the CDE bit
enables oscillator fail detection
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