INDEX61075MHZ Datasheet, PDF (1/48 Pages) Intel Corporation – PENTIUM PROCESSOR at iCOMP INDEX 61075 MHz

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PENTIUM® PROCESSOR at iCOMP® INDEX 610\75 MHz
n Compatible with Large Software Base
− MS-DOS*, Windows*, OS/2*, UNIX*
n 32-Bit CPU with 64-Bit Data Bus
n Superscalar Architecture
− Two Pipelined Integer Units Are
Capable of 2 Instructions/Clock
− Pipelined Floating Point Unit
n Separate Code and Data Caches
− 8K Code, 8K Writeback Data
− MESI Cache Protocol
n Advanced Design Features
− Branch Prediction
− Virtual Mode Extensions
n 3.3V BiCMOS Silicon Technology
n 4M Pages for Increased TLB Hit Rate
n IEEE 1149.1 Boundary Scan
n Internal Error Detection Features
n SL Enhanced Power Management
Features
− System Management Mode
− Clock Control
n Fractional Bus Operation
− 75-MHz Core / 50-MHz Bus
The Pentium^® processor is fully compatible with the entire installed base of applications for DOS*, Windows*,
OS/2*, and UNIX*, and all other software that runs on any earlier Intel 8086 family product. The Pentium
processor’s superscalar architecture can execute two instructions per clock cycle. Branch prediction and
separate caches also increase performance. The pipelined floating-point unit delivers workstation level
performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The
Pentium processor (610\75) has 3.3 million transistors, is built on Intel’s advanced 3.3V BiCMOS silicon
technology, and has full SL Enhanced power management features, including System Management Mode
(SMM) and clock control. The additional SL Enhanced features, 3.3V operation, and the TCP package, which
are not available in the Pentium processor (510\60, 567\66), make the Pentium processor (610\75) TCP ideal for
enabling mobile Pentium processor designs. The Pentium processor may contain design defects or errors
known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available upon request.
June 1997
Order Number 242323-004