FW80321M400 Datasheet, PDF (1/54 Pages) Intel Corporation – 80321 I/O Processor

Intel^® 80321 I/O Processor
Datasheet
Product Features
■ Core Features
— Integrated Intel^® XScale^™ Core
— ARM* V5T Instruction Set
— ARM V5E DSP Extensions
— 400 MHz and 600 MHz
— Write Buffer, Write-back Cache
■ PCI Bus Interface
— PCI Local Bus Specification, Rev. 2.2
compliant
— PCI-X Addendum to the PCI Local Bus
Specification, Rev. 1.0a
— 64-bit/66 MHz Operation in PCI Mode
—64-bit/133 MHz Operation in PCI-X
Mode
■ DMA Controller
— Two Independent Channels Connected
to Internal Bus
— Up to 1064 Mbytes/s Burst Support in
PCI-X Mode
— Up to 1600 Mbytes/s Burst Support for
Internal Bus
— Two 1-Kbyte Queues in Ch-0 and Ch-1
— 2³² Addressing Range on Internal Bus
Interface
— 2⁶⁴ Addressing Range on PCI Interface
■ Application Accelerator Unit
— Performs XOR on Read Data
— Compute Parity Across Local Memory
Blocks
— Support 32-bit PCI Initiators and Targets — 1 Kbyte/512-byte Store Queue
— Four Split Read Requests as Initiator
— Eight Split Read Requests as Target
■ I²C Bus Interface Units
— Two Separate I²C Units
— 64-bit Addressing Support
— Serial Bus
■ Memory Controller
— Master/Slave Capabilities
—PC200 Double Data Rate (DDR) SDRAM ^{— System Management Functions}
— Up to 1 Gbyte of 64-bit DDR SDRAM
— Up to 512 Mbytes of 32-bit DDR
SDRAM
■ SSP Serial Port
— Full-duplex Synchronous Serial Interface
— Supports 7.2 KHz to 1.84 MHz Bit Rates
— Single-bit Error Correction, Multi-bit
Support (ECC)
— 1024-byte Posted Memory Write Queue
— 40- and 72-bit wide Memory Interface
■ Address Translation Unit
— 2 Kbyte or 4 Kbyte Outbound Read
Queue
■ Peripheral Performance Monitoring Unit
— One Dedicated Global Time Stamp
Counter
— Fourteen Programmable Event Counters
— Three Control/Status Registers
■ Timers
— Two Dual-programmable 32-bit Timers
— 4 Kbyte Outbound Write Queue
— Watchdog Timer
— 4 Kbyte Inbound Read and Write Queue ^{■ 544-Ball, Plastic Ball Grid Array (PBGA)}
—Connects Internal Bus to PCI/PCI-X Bus ^{■ Eight General Purpose I/O Pins}
Document Number: 273518-005
January 2005