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A80960CF33 Datasheet, PDF (1/70 Pages) Intel Corporation – 80960CF-40, -33, -25 32-Bit High-Performance Superscalar Embedded Microprocessor | |||
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80960CF-40, -33, -25
32-Bit High-Performance Superscalar
Embedded Microprocessor
Product Features
s Socket and Object Code Compatible with 80960CA
s Two Instructions/Clock Sustained Execution
s Four 71 Mbytes/s DMA Channels with Data Chaining
s Demultiplexed 32-Bit Burst Bus with Pipelining
Datasheet
s 32-Bit Parallel Architecture
â Two Instructions/clock Execution
â Load/Store Architecture
â Sixteen 32-Bit Global Registers
â Sixteen 32-Bit Local Registers
â Manipulates 64-Bit Bit Fields
â 11 Addressing Modes
â Full Parallel Fault Model
â Supervisor Protection Model
s Fast Procedure Call/Return Model
â Full Procedure Call in 4 Clocks
s On-Chip Register Cache
â Caches Registers on Call/Ret
â Minimum of 6 Frames Provided
â Up to 15 Programmable Frames
s On-Chip Instruction Cache
â 4 Kbyte Two-Way Set Associative
â 128-Bit Path to Instruction Sequencer
â Cache-Lock Modes
â Cache-Off Mode
s High Bandwidth On-Chip Data RAM
â 1 Kbyte On-Chip Data RAM
â Sustains 128 bits per Clock Access
s Selectable Big or Little Endian Byte
Ordering
s Four On-Chip DMA Channels
â 71 Mbytes/s Fly-by Transfers
â 40 Mbytes/s Two-Cycle Transfers
â Data Chaining
â Data Packing/Unpacking
â Programmable Priority Method
s 32-Bit Demultiplexed Burst Bus
â 128-Bit Internal Data Paths to and from
Registers
â Burst Bus for DRAM Interfacing
â Address Pipelining Option
â Fully Programmable Wait States
â Supports 8-, 16- or 32-Bit Bus Widths
â Supports Unaligned Accesses
â Supervisor Protection Pin
s High-Speed Interrupt Controller
â Up to 248 External Interrupts
â 32 Fully Programmable Priorities
â Multi-mode 8-Bit Interrupt Port
â Four Internal DMA Interrupts
â Separate, Non-maskable Interrupt Pin
â Context Switch in 625 ns Typical
s On-Chip Data Cache
â 1 Kbyte Direct-Mapped, Write Through
â 128 bits per Clock Access on Cache Hit
Order Number: 272886-002
September 2002
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