87C196LA Datasheet, PDF (1/21 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

PRODUCT PREVIEW
87C196LA
CHMOS 16-BIT MICROCONTROLLER
Automotive
s 20 MHz operation^†
s 24 Kbytes of on-chip OTPROM
s 768 bytes of on-chip register RAM
s Register-to-register architecture
s Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
s Six-channel/10-bit A/D with sample and
hold
s High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
† _{16 MHz standard; 20 MHz is speed premium}
s Full-duplex serial I/O port with
dedicated baud-rate generator
s Enhanced full-duplex, synchronous
serial I/O port (SSIO)
s Programmable 8- or 16-bit external bus
s Optional clock doubler with
programmable clock output signal
s SFR register that indicates the source
of the last reset
s Design enhancements for EMI
reduction
s Oscillator failure detection circuitry
s Watchdog timer (WDT)
s –40° C to +125° C ambient temperature
s 52-pin PLCC package
NOTE
This datasheet contains information on products in the design phase of development.
The specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed
core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a
dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave
transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with
prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture
and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis-
ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock
doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock
speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices
where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O
ports are driven low at reset, avoiding the need for pull-up resistors.
COPYRIGHT © INTEL CORPORATION, 1996
October 1996
Order Number: 272806-001