21555 Datasheet, PDF (1/2 Pages) Intel Corporation – Non-Transparent PCI-to-PCI Bridge

developer.intel.com
product brief
21555 Non-Transparent
PCI-to-PCI Bridge
Revolutionary Bridge Technology for Intelligent I/O
and Embedded Applications
Product Highlights
s Non-Transparent PCI-to-PCI bridge
technology for high-performance embedded
and intelligent I/O applications
s Independent address spaces and asynchronous
clocks deliver unparalleled application
flexibility
s 64-bit primary and secondary bus interfaces
deliver high performance for data-intensive
applications
s Compliant with ACPI and PCI bus power
management specifications
s Secondary bus arbitration support for up to
nine bus master devices
s Evaluation Design Kit speeds time-to-market
s Fully compliant with Revision 2.3 of the PCI
specification including delayed transactions
s Available in 33 and 66 MHz
Product Overview
Intel’s 21555 Non-Transparent PCI-to-PCI
bridge chip enables add-in card vendors to
deliver high-performance, intelligent option
cards and embedded products that previously
were not possible. Designed specifically for
applications where a processor is used behind a
PCI-to-PCI bridge, the 21555 provides a clean
architecture for creating a product with multiple
processor domains.
A Unique Bridge Architecture
Intel’s 21555 is a unique new Non-Transparent
PCI-to-PCI bridge solution. The 21555 provides
designers of intelligent controllers and
embedded systems with a Non-Transparent PCI-
to-PCI bridge solution capable of resolving
resource conflicts between a PCI-based host
system and a PCI-based subsystem. This gives a
local processor maximum flexibility in mapping
and managing subsystem resources.
Efficient Management of System and
Subsystem Resources
The 21555 provides independent primary and
secondary address spaces, which allow
independent host and local address mapping.
With this key feature, local memory requirements
need not impact the host address map. The 21555
performs address translation between the primary
and secondary buses, resolving address resource
conflicts between the host and local address
domains.
Featuring a subsystem PCI configuration
boundary, the 21555 allows the local processor to
have complete PCI configuration control of
subsystem devices, without host interference. This
advanced feature also allows the 21555 to present
a subsystem, such as a RAID controller, as a
single virtual PCI device. An added benefit of
this design is the ability to easily identify a single
device driver for the entire subsystem. Another
feature of the 21555, a serial ROM interface,
allows manufacturers to customize the 21555 for
a particular application by pre-loading the ROM
with vendor-specific configuration data.