IN74AC533 Datasheet, PDF (4/5 Pages) Integral Corp. – Octal 3-State Inverting Transparent Latch High-Speed Silicon-Gate CMOS

IN74AC533
AC ELECTRICAL CHARACTERISTICS(C_L=50pF, Input t_r=t_f=3.0 ns)
Symbol
Parameter
V_CC*
Guaranteed Limits
V
25 °C
-40°C to
Unit
85°C
Min Max Min Max
t_PLH Propagation Delay, Input D to Q (Figure 1)
3.3 2.0 14.0 1.5 16.0 ns
5.0 2.0 10.0 1.5 11.0
t_PHL Propagation Delay, Input D to Q (Figure 1)
3.3 2.0 13.0 1.5 14.5 ns
5.0 2.0 9.5 1.5 10.5
t_PLH Propagation Delay, Latch Enable to Q (Figure 3.3 2.0 14.0 1.5 16.5 ns
2)
5.0 2.0 10.0 1.5 11.5
t_PHL Propagation Delay, Latch Enable to Q (Figure 3.3 2.0 13.0 1.5 14.5 ns
2)
5.0 2.0 10.0 1.5 11.0
t_PZH Propagation Delay, Output Enable to Q
(Figure 3)
3.3 2.0 12.5 1.5 14.0 ns
5.0 2.0 9.5 1.5 10.5
t_PZL Propagation Delay, Output Enable to Q
(Figure 3)
3.3 2.0 12.5 1.5 14.0 ns
5.0 2.0 9.5 1.5 10.5
t_PHZ Propagation Delay, Output Enable to Q
(Figure 3)
3.3 2.0 13.0 1.5 14.5 ns
5.0 2.0 10.0 1.5 11.0
t_PLZ Propagation Delay, Output Enable to Q
(Figure 3)
3.3 2.0 13.0 1.5 14.5 ns
5.0 2.0 10.0 1.5 11.0
C_IN Maximum Input Capacitance
5.0
4.5
4.5
pF
C_PD Power Dissipation Capacitance
*_{Voltage Range 3.3 V is 3.3 V ±0.3 V}
Voltage Range 5.0 V is 5.0 V ±0.5 V
Typical @25°C,V_CC=5.0 V
40
pF
TIMING REQUIREMENTS(C_L=50pF,Input t_r=t_f=3.0 ns)
Symbol
Parameter
V_CC*
V
t_su
Minimum Setup Time, Input D to Latch
3.3
Enable (Figure 4)
5.0
t_h
Minimum Hold Time, Latch Enable to
3.3
Input D (Figure 4)
5.0
t_w
Minimum Pulse Width, Latch Enable
3.3
(Figure 2)
5.0
*_{Voltage Range 3.3 V is 3.3 V ±0.3 V}
Voltage Range 5.0 V is 5.0 V ±0.5 V
Guaranteed Limits
25 °C
-40°C to
Unit
85°C
5.5
6.0
ns
4.0
4.5
1.5
1.0
ns
1.5
1.0
6.0
6.5
ns
4.5
5.0
439