IW4042B Datasheet, PDF (1/5 Pages) Integral Corp. – QUAD CLOCKED LATCH

IW4042B
QUAD CLOCKED «D» LATCH
High-Voltage Silicon-Gate CMOS
CD4042B types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p-channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are
present. When a CLOCK transition occurs (positive for
POLARITY = 0 and negative for POLARTY = 1) the information
present at the input during the CLOCK transition is retained at
the outputs until an opposite CLOCK transition occurs.
The CD4042B types are supplied in 16-lead hermetic dual-in-
line ceramic packages (D and F suffixes); 16-lead dual-in-line
plastic package (E suffix), and in chip form (H suffix).
• Operating Voltage Range: 3.0 to 18 V
ORDERING INFORMATION
IW4042BN Plastic
IW4042BD SOIC
T_A = -55° to 125° C for all
packages
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
PIN ASSIGNMENT
2.5 V min @ 15.0 V supply
Q4 1
16 VCC
Q1 2
15 Q4
Q1 3
14 D4
LOGIC DIAGRAM
D1 4
13 D3
CLOCK 5
12 Q3
POLARITY 6
11 Q3
D2 7
10 Q2
GND 8
9 Q2
PIN 16 =V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Clock Polarity
Q
0
0
D
1
0
Latch
1
1
D
0
1
Latch
1