IW4015B Datasheet, PDF (1/5 Pages) Integral Corp. – Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS

TECHNICAL DATA
Dual 4-Stage Static Shift Register
High-Voltage Silicon-Gate CMOS
IW4015B
The IW4015B consists of two identical, independent, 4-stage
serial-input/parallel-output registers. Each register has independent
CLOCK and RESET inputs as well as a single serial DATA input. “Q”
outputs are available from each of the four stages on both registers. All
register stages are D-type, master-slave flip-flops. The logic level
present at the DATA input is transferred into the first register stage and
shifted over one stage at each positive-going clock transition. Resetting
of all stages is accomplished by a high level on the reset line. Register
expansion to 8 stages using one IW4015B package, or to more than 8
stages using additional IW4015B’s is possible.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4015BN Plastic
IW4015BD SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8= GND
24
FUNCTION TABLE
Inputs
Clock Data Reset
L
L
HL
XL
X XH
Outputs
Q1 Q_n
L Q_n-1
H Q_n-1
No change
LL
X = don’t care