IN74LV74 Datasheet, PDF (1/7 Pages) Integral Corp. – Dual D-type flip-flop with set and reset; positive-edge trigger

TECHNICAL DATA
IN74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S_D) and (R_D) inputs;
also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action in
the clock input makes the circuit highly tolerant to slower clock rise and
fall times.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC_S
• Supply voltage range: 1.2 to 3.6 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
N SUFFIX
PLASTIC
14
1
D SUFFIX
14
1
SOIC
ORDERING INFORMATION
IN74LV74N
IN74LV74D
IZ74LV74
Plastic DIP
SOIC
chip
T_A = -40° to 125° C for all packages
PIN ASSIGNMENT
RESET 1 1
DATA 1 2
CLOCK 1 3
SET 1 4
Q1 5
Q1 6
GND 7
14 V _CC
13 RESET 2
12 DATA2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
PIN 20=V_CC
PIN 10 = GND
INTEGRAL
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X H* H*
HH
H
H
L
HH
L
L
H
HH
L
X No Change
HH
H
X No Change
HH
X No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don’t care
Z = high impedance
1