IN74LS164 Datasheet, PDF (1/4 Pages) Integral Corp. – 8-Bit Serial-Input/Parallel-Outpout Shift Register

TECHNICAL DATA
8-Bit Serial-Input/Parallel-Output
Shift Register
IN74LS164
This 8-bit shift register features gated serial inputs and an
asynchronous reset. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip flop to the low level at the
next clock pulse. A high level input enables the other input which will
then determine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is high or low, but only information
meeting the setup requirements will be entered clocking occurs or the
low-to-high level transition of the clock input. All inputs are diode-
clamped to minimize transmission-line effects.
• Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Asynchronous Clear
ORDERING INFORMATION
IN74LS164N Plastic
IN74LS164D SOIC
T_A =0° to 70°C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 14 =V_CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Outputs
Reset Clock A1 A2 Q_A Q_B ... Q_H
L
X
X X L L ... L
H
XX
no change
H
HD
D Q_An ... Q_Gn
H
DH
D Q_An ... Q_Gn
H
LL
L Q_An ... Q_Gn
D = data input
X = don’t care
Q_An - Q_Gn = data shifted from the previous stage on a
rising edge at the clock input.
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