IN74HCT373A Datasheet, PDF (1/5 Pages) Integral Corp. – Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
IN74HCT373A
The IN74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High-Speed CMOS inputs.
The IN74HCT373A is identical in pinout to the LS/ALS373.
The eight latches of the IN74HCT373A are transparent D-type
latches. While the Latch Enable is high the Q outputs follow the Data
Inputs. When Latch Enable is taken low, data meeting the setup and
hold times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not
enabled.
• TTL/NMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT373AN Plastic
IN74HCT373ADW SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Latch D
Enable Enable
L
H
H
L
H
L
L
L
X
H
X
X
X = Don’t Care
Z = High Impedance
Output
Q
H
L
No Change
Z
371