IN74HCT109 Datasheet, PDF (1/5 Pages) Integral Corp. – DUAL J-K FLIP-FLOP WITH SET AND RESET

IN74HCT109
DUAL J-K FLIP-FLOP
WITH SET AND RESET
High-Performance Silicon-Gate CMOS
The IN74HCT109 is identical in pinout to the LS/ALS109. The
IN74HCT109 may be used as a level converter for interfacing
TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J- K flip-flops with individual set,
reset, and clock inputs. Changes at the inputs are reflected at the
outputs with the next low-to-high transition of the clock. Both Q to
Q outputs are available from each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT109N Plastic
IN74HCT109D SOIC
T_A = -55° to 125° C for all
packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Output
Set Reset Clock J _K Q _Q
LH
X XXHL
H
L
L
L
X XXLH
X
X X H^* H^*
HH
L L LH
HH
H L Toggle
HH
LH
No
Change
HH
HHH L
HH
L XX
No
Change
X = Don’t care
*_{Both outputs will remain high as long as}
Set and Reset are low., but the output
states are unpredictable if Set and Reset
go high simultaneously.
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