IN74HC74 Datasheet, PDF (1/5 Pages) Integral Corp. – Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

TECHNICAL DATA
Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
IN74HC74A
The IN74HC74A is identical in pinout to the LS/ALS74. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset,
and Clock inputs. Information at a D-input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip-flop. The Set
and Reset inputs are asynchronous.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC74AN Plastic
IN74HC74AD SOIC
T_A = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =V_CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q Q
LH
X
XH L
HL
X
XLH
L
L
X
X
H^*
H^*
HH
HH L
HH
L
L
H
HH
L
X No Change
HH
H
X No Change
HH
X No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care
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