IN74HC193 Datasheet, PDF (1/7 Pages) Integral Corp. – Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS

TECHNICAL DATA
IN74HC193
Presettable 4-Bit Binary UP/DOWN Counter
High-Performance Silicon-Gate CMOS
The IN74HC193 is identical in pinout to the LS/ALS193. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset inputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TC_D) and Terminal Count Up (TC_U) Outputs are provided to
enable cascading of both up and down counting functions. The TC_D
output produces a negative going pulse when the counter underflows
and TC_U outputs a pulse when the counter overflows. The counter can
be cascaded by connecting the TC_U and TC_D outputs of one device to
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC193N Plastic
IN74HC193D SOIC
T_A = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V_CC
PIN 8 = GND
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