IN74AC175 Datasheet, PDF (1/5 Pages) Integral Corp. – Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS

TECHNICAL DATA
Quad D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
IN74AC175
The IN74AC175 is identical in pinout to the LS/ALS175,
HC/HCT175. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive-going edge of the Clock input.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC175N Plastic
IN74AC175D SOIC
T_A = -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
264
FUNCTION TABLE
Inputs
Outputs
Reset Clock
D
QQ
L
X
X
LH
H
H
HL
H
L
LH
H
L
X no change
X = Don’t care