IA59032_08 Datasheet, PDF (9/19 Pages) InnovASIC, Inc – 32-Bit High-Speed Microprocessor Slice

IA59032
32-Bit High-Speed Microprocessor Slice
Data Sheet
August 19, 2008
The ALU data output is routed to several destinations. It can be a data output of the device and it
can also be stored in the RAM or the Q register. Eight possible combinations of ALU destination
functions are available, as defined by the I(8:6) inputs.
The 32-bit data output field (Y) features three-state outputs. An output control (OEn) is used to
enable the three-state outputs. When OEn is HIGH, the Y outputs are in the high-impedance state.
A two input mux is also used at the data output such that either the A-port of the RAM or the ALU
outputs (F) are selected at the device Y outputs. I(8:6) inputs control this selection.
As was discussed previously, the RAM inputs are driven from a three-input mux. This allows the
ALU outputs to be entered non-shifted, shifted up one position (X2) or shifted down one position
(/2). The shifter has two ports; one is labeled RAM0 and the other is RAM31. Both of these ports
consist of a buffer driver with a three-state output and an input to the mux. Thus, in the shift up
mode, the RAM31 buffer is enabled and the RAM0 mux input is enabled. Likewise, is in the shift
down mode, the RAM0 buffer and RAM31 input are enabled. In the no-shift mode, both buffers
are in the high-impedance state and the mux inputs are not selected. The I(8:6) inputs control the
shifter.
Similarly, the Q register is driven from a 3-input mux. In the no-shift mode, the mux enters the
ALU data into the Q register. In either the shift-up or shift-down mode, the mux selects the Q
register data appropriately shifted up or down. The Q shifter also has two ports; Q0 and Q31. The
operations of these two ports are similar to the RAM shifter and are also controlled from the I(8:6)
inputs.
The clock input controls the RAM, Q register, and the A and B data latches. When enabled, data is
clocked into the Q register on the LOW to HIGH transition of the clock. When CP is HIGH, the
A and B latches are open and will pass whatever data is present at the RAM outputs. When CP is
LOW, the latches are closed and will retain the last data entered. New data will be written into the
RAM defined by the B address field when the clock input is LOW.
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