IA2910A Datasheet, PDF(9/19 Page) InnovASIC, Inc

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IA2910A Datasheet, PDF (9/19 Pages) InnovASIC, Inc – Microprogram Controller

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IA2910A

Microprogram Controller

Page 9 of 19

Preliminary Data Sheet

Instruction 4 PUSH is the PUSH/CONDITIONAL LOAD COUNTER instruction and is used

primarily for setting up loops in microprogram firmware. In Figure II, when instruction 52 is in the

pipeline register, a PUSH will be made onto the stack and the counter will be loaded based on the

condition. When a PUSH occurs, the value pushed is always the next sequential instruction address.

In this case, the address is 53. If the test fails, the counter is not loaded; if it is passed, the counter

is loaded with the value contained in the pipeline register branch address field. Thus, a single

microinstruction can be used to set up a loop to be executed a specific number of times.

Instruction 8 will describe how to use the pushed value and the register/counter for looping.

Instruction 5 JSRP is a CONDITIONAL JUMP-TO-SUBROUTINE via the register/counter or

the contents of the PIPELINE register. As shown in Figure II, a PUSH is always performed and

one of two subroutines executed. In this example, either the subroutine beginning at address 80 or

the subroutine beginning at address 90 will be performed. A return-from-subroutine (instruction

10) returns the microprogram flow to address 55. In order for this microinstruction control

sequence to operate correctly, both the next address fields of instruction 53 and 54 would have to

contain the proper value. Letâs assume that the branch address fields of instruction 53 contain the

value 90 so that it will be in the IA2910A register/counter when the contents of address 54 are in

the pipeline register. This requires that the instruction at address 53 load the register/counter.

Now, during the execution of instruction 5 (at address 54), if the test failed, the contents of the

pipeline register contents (value = 80) will determine the address of the next microinstruction.

Therefore, this instruction provides the ability to select one of two subroutines to be executed

based on a test condition.

Instruction 6 CJV is a CONDITIONAL JUMP VECTOR instruction which provides the

capability to take the branch address from a third source heretofore not discussed. In order for this

instruction to be useful, the IA2910A output, VECTn is used to control a three-state control input

of a register, buffer, or PROM containing the next microprogram address. This instruction

provides one technique for performing interrupt type branching at the microprogram level. Since

this instruction is conditional, a pass causes the next address to be taken from the vector source,

while failure causes the next address to be taken from the microprogram counter. In the example

of Figure II, if the CJV instruction is contained at location 52, execution will continue at vector

address 20 if the CCn input is LOW and the microinstruction at address 53 will be executed if the

CCn input is HIGH.

Instruction 7 JRP is a CONDITIONAL JUMP via the contents of the IA2910A register/counter

or the contents of the pipeline register. This instruction is very similar to instruction 5; the

conditional jump-to-subroutine via R or PL. The major difference between instruction 5 and

instruction 7 is that no push onto the stack is performed with 7. Figure II depicts this instruction

as a branch to one of two locations depending on the test condition. the example assumes the

pipeline register contains the value 70 when the contents of address 52 is being executed. As the

contents of address 53 is clocked into the pipeline register, the value 70 is loaded into the

pipeline register. Thus, control is transferred to either address 70 or address 80 depending on the

test condition.

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