IA82050 Datasheet, PDF (6/11 Pages) InnovASIC, Inc – ASYNCHRONOUS SERIAL CONTROLLER

IA82050
ASYNCHRONOUS SERIAL CONTROLLER
DC Characteristics
Data Sheet
As of Production Ver. 01
Symbol
V_IL
V_IH1
V_IH2
V_OL
V_OH
I _LI
I _LO
I _CC
I _PU
I _STBY
I _OHR
I _OLR
C_IN
C_IO
C_XTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2), (8)
(3), (8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min
Max
Unit
-0.5
0.7
V
2.1
V_DD+.07
V
2.1
V_DD+.07
V
0.4
V
2.4
V
±1
µA
±1
µA
1.12 ^mA/MHz
-283
-137
A
100
µA
1.92
mA
N/A
mA
5
pF
6
pF
6
pF
NOTES:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @ I_OL = 1.92 mA
3. @ I_OH = 1.92 mA
4. 0< V_IN < V_CC .
5. 0.4V < V_OUT < V_CC - 0.4V
6. V _DD = 5.5V, V_IL= 0.7V (max), V_IH = V_DD - 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X CLK, I_OL = I_OH = 0.
7. Freq. = 1MHz.
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
Static IDD current is exclusive of input/output drive requirements and is
9. Freq. = 1MHz. But, input clock not running.
measured with the clocks stopped and all inputs tied to VDD or VSS, configured
to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ V_in = 0.0V V_DD = 5.5V
Copyright © 2001
innovASIC

The End of Obsolescence™
ENG211010326-00
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