IA82050_11 Datasheet, PDF (11/22 Pages) InnovASIC, Inc – Asynchronous Serial Controller

IA82050
Asynchronous Serial Controller
4. Register Descriptions
Data Sheet
February 25, 2011
4.1 Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL)
Baud Rate Generator A Divide Count (MSB and LSB) – When generating TXCLK or RXCLK,
the selected source clock will be divided by this value (ADDR 001/000, Mode R/W, Default
00000000/00000010).
4.2 General Interrupt Enable Register (GER)
Enables the general categories of interrupts when generating INT (ADDR 001, Mode R/W,
Default 00000000).
Table 2. General Interrupt Enable Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0 MIE RXIE TFIE RFIE
MIE
RXIE
TFIE
RFIE
Modem Interrupt Enable, 1=Enabled, 0=Disabled
Receive Interrupt Enable, 1=Enabled, 0=Disabled
Transmit FIF0 Interrupt Enable, 1=Enabled, 0=Disabled
Receive FIFO Interrupt Enable, 1=Enabled, 0=Disabled
4.3 General Interrupt Register (GIR)
Read-only interrupt register containing priority encoded enabled interrupt vector and interrupt
pending flag. Writes to this register only affect Bank Pointer bits (ADDR 010, Mode R, Default
00000001).
Table 3. General Interrupt Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 BANK1 BANK0 0 0 BI1 BI0 IPN
BANK1, BANK0 – Bank Pointer – not used in IA82050, user must ensure these bits are never written
BI1, BI0 – Interrupt Vector
11=Receive Interrupt (highest priority)
10=Receive FIFO Interrupt
01=Transmit FIF0 Interrupt
00=Modem Interrupt (lowest priority)
IPN – Interrupt Pending (1=no interrupt pending, 0=interrupt pending)
4.4 Line Configure Register (LCR)
Defines configuration of serial message (ADDR 011, Mode R/W, Default 00000000).
®
IA211030617-08
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 11 of 22
1-888-824-4184