IA64250_08 Datasheet, PDF (11/24 Pages) InnovASIC, Inc – Histogram/Hough Transform Processor

IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
io(1:0) Control the operations of the ACC and LUT RAMs during I/O mode (when the
STARTIOn signal has been asserted).
io0
io1
FUNCTION
0
0
transfer data from the ACC RAM to the LUT RAM
0
1
read the ACC RAM
1
0
read the LUT RAM
1
1
write the LUT RAM
hclr(1:0) Control the clearing of the ACC RAM during I/O mode
hclr0
0
0
1
1
hclr1
0
1
0
1
FUNCTION
ACC RAM cleared when either the ACC RAM or LUT RAM is
accessed
Undefined
ACC RAM cleared only when the ACC RAM is accessed
ACC RAM not cleared during an i/o operation
func Determines the function performed by the marker processor. When high, each marker
circuit within the processor will locate an accumulated count from the ACC RAM
corresponding to the previously given grey value. When low, each marker will locate the
grey value corresponding to a previously given accumulation count from the ACC RAM.
pdwn When high, the ACC and LUT RAMs are placed in an inactive mode. Should be low for
normal operation.
Memory Configurations
The following memory maps specify the configuration of the ACC RAM and the LUT RAM in the
various computational modes.
ACC RAM Histogram Mode:
Grey Level
0
1
.
.
.
.
511
Memory Contents
Count for Grey Value 0
Count for Grey Value 1
.
.
.
.
Count for Grey Value 511
IA211011114-01
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