PEB22504 Datasheet, PDF (96/128 Pages) Infineon Technologies AG – Quad Line Interface Unit for E1⁄T1⁄J1 QuadLIU

Code Violation Counter (Read)
Addresses CVCL: 19_H, 39_H, 59_H, 79_H
Addresses CVCH: 1A_H, 3A_H, 5A_H, 7A_H
7
CVCL CV7
PEB 22504
QuadLIU V1.1
Register Description
0
CV0
7
0
CVCH CV15
CV8
CV(15:0)
Code Violations
E1 mode:
If the HDB3 or the CMI code is selected, the 16-bit counter is
incremented if violations of the HDB3 code are detected. The error
detection mode is determined by programming the bit LIM0.EXZE.
If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar
violations are counted.
T1 mode:
If the B8ZS code (bit LIM0.RC(1:0) = 10, GCR2.PMODx = 1) is
selected, the 16-bit counter is incremented upon detection of
violations that are not due to zero substitution. If LIM0.EXZE is set,
excessive zero strings (more than seven contiguous zeros) are
detected and counted.
If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar
violations are counted. If LIM0.EXZE is set, excessive zero strings
(more than 15 contiguous zeros) are detected and counted.
During alarm simulation, the counter is incremented every four bits
received up to its saturation.
Clearing and updating the counter is done according to bit LIM1.ECM.
If this bit is cleared, the error counter buffer is permanently updated.
For correct read access of the error counter, bit CMDR.DCVC has to
be set. With the rising edge of this bit, updating of the buffer is stopped
and the error counter is cleared. Bit CMDR.DCVC is reset
automatically with a read access to the error counter high byte.
If LIM1.ECM is set every second (interrupt ISR1.SEC), the error
counter is latched and then reset automatically. The latched error
counter state has to be read within the next second.
Data Sheet
96
2001-02