TLE8209-2SA_12 Datasheet, PDF (9/38 Pages) Infineon Technologies AG – SPI Programmable H-Bridge

TLE8209-2SA
Power Supply
5
Power Supply
5.1
Basic Supply Characteristics
The TLE8209-2SA has three different supply pins: VDD, VS and VDDIO. VDD is used to supply the internal logic
circuitry. VS connects to battery voltage and supplies the output stages. The voltage at pin VDDIO defines the high
level output voltage at the pin SO of the SPI interface. VDDIO is also used as a mode select pin. If VDDIO is
connected to ground, the device is set to status flag mode (SPI inactive).
On power up the device will enter a functional state when V_DD rises above the functional reset threshold V_{DD_RES}.
In this state all output stages are inactive and internal registers are cleared. When V_DD rises further above the
power on reset threshold V_{DD_POR} the device starts operation with a delay time of t_POR.
5.2
VDD Monitoring
The logic supply voltage level at the pin VDD is monitored. If the voltage at pin V_DD is out of the permissible range
of V_{DD_L} … V_{DD_H} the power stages of TLE8209-2SA are switched off and pin ABE is pulled to ground. To suppress
glitches in the V_DD monitoring, a glitch filter is implemented.V_DD is measured with reference to pin GNDABE. The
state of VDD monitoring is stored in STATCON_REG and can be read out via SPI.
The output stages can also be turned off by pulling the ABE pin to ground externally.
In case of VDD failure, the output stages are switched off, even if the pin ABE should be connected to a high level
signal because of external short circuit to VDD or battery voltage (up to 18V). OUT1 and OUT2 cannot be switched
on in over- or undervoltage condition, switching off is always possible. A power on reset (V_DD < V_{DD_POR}) switches
off all stages without delay.
Control of VDD-monitoring is possible in SPI mode only. Detailed information (differentiation of over and under-
voltage detection) is only possible by SPI interface.
Behavior of VDD monitoring in SF mode:
- monitoring is present with the specified values for over- and undervoltage
- any test of over- and undervoltage threshold is not possible
- the latch for overvoltage is disabled
VDD Undervoltage
If the VDD voltage is lower than the supply voltage supervisory lower threshold (V_{DD_THL}), output stages are shut
off after a filtering time (t_{FIL_OFF}) and the bi-directional pin ABE is pulled low. At the transition from undervoltage to
normal voltage the signal at pin ABE goes high and the output stages will return to normal operation after a filtering
time (t_{FIL_ON}) has expired. For output control via SPI the bits MUX and SINx in the config register have to be re-
programmed. New failures are not stored to diagnostic registers during undervoltage, register content remains
valid, writing new information to configuration registers is possible as far as they are not reset by ABE. If VDD falls
below the power-on-reset supply voltage (V_{DD_POR}) all stages are shut off and ABE is switched active low. When
VDD is rising above the power-on-reset supply voltage threshold (V_{DD_POR}) a power-on-reset is generated (t_POR),
setting all registers to its default state.
VDD Overvoltage
If the VDD voltage is higher than the supply voltage supervisory upper threshold (V_{DD_THH}), all output stages are
shut off after a filtering time (t_{FIL_OFF}) and the bi-directional pin ABE is pulled low. The behavior of the ABE level
and output stages on the return of VDD from overvoltage to the correct range is configured in STATCON_REG,
bit CONFIG0)
CONFIG0=’1’: ABE is latched and outputs remain off after overvoltage. Return to normal operation is only possible
with power-on reset or by changing this bit via SPI.
Data Sheet
9
Rev. 1.2, 2012-12-20