TLE4290 Datasheet, PDF (9/18 Pages) Infineon Technologies AG – 5-V Low-Drop Voltage Regulator

TLE 4290
The power good circuit supervises the output voltage. In case V_Q falls below the Power
Good switching threshold the Power Good output PG is set LOW after the power good
reaction time. The power good LOW signal is generated down to an output voltage V_Q
to 1 V. A LOW signal at the power good pin informs that the battery was lost and memory
is no longer valid.
The feature should only be used in combination to a microcontroller with internal reset.
For the power good delay time after the output voltage of the regulator is above the reset
threshold, the reset signal is set High again. The reset delay time is defined by the reset
delay capacitor C_D at pin D.
The Power Good delay time is defined by the charging time of an external delay
capacitor C_D.
C_D= (t_rd × I_D,c) / ∆V
With
C_D Power Good delay capacitor
t_rd Power Good delay time
∆V = V_DU, typical 1.8 V
I_D,c Charge current typical 6 µA
V_Ι
V_Q
V_D
t _rd
t _rr
V _PG
< t _rr
V _{Q,pgt_i}
V _{Q,pgt_d}
dV
dt
=
Ι_{D, c}
C_D
V_DU
V _DL
Power-on
Power Good
Signal
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage Secondary Overload
Spike at Output
AED03074
Figure 5 Power Good Timing
Data Sheet Rev. 1.4
9
2001-10-18