ISO1H815G Datasheet, PDF (9/20 Pages) Infineon Technologies AG – Coreless Transformer Isolated Digital Output 8 Channel 1.2A High-Side Switch

ISOFACE^TM
ISO1H815G
Functional Description
3.5
Parallel Interface
The ISO1H815G contains a parallel interface that can
be directly controlled by the microcontroller output
ports. The parallel interface can also be switched over
to a direct control that allows direct changes of the
outputs OUT0 ... OUT7 by means of the corresponding
inputs D0 ... D7 without additional logic signals. To
activate the parallel direct control mode pin CS and pin
WR have to be connected both to ground.
3.5.1
Parallel Interface Signal
Description
CS - Chip select. The system microcontroller selects
the ISO1H815G by means of the CS pin. Whenever the
pin is in a logic low state, data can be transferred from
the µC.
CS High to low transition:
• Parallel input data can be written in from then on
CS Low to high transition:
3.5.2 uC Control Mode
AD0
CS
WR
WR
P0
P1
P2
P3
P4
P5
P6
P7
µC (i.e C166)
D0
D1
D2
Output lines
D3
D4
D5
D6
D7
DIAG
Parallel
Interface
IC1
Number of adressed ICs = n
Number of necessary control and data ports = 9 n
Individual ICs are adressed by the chip select
Figure 9 Parallel bus configuration
• The data in the input latches is transferred to the
output buffer
WR - Write. The system controller enables the write
procedure in the ISO1H815G by means of the signal
WR. A logic low state signal at pin WR writes the input
data into the input latches when the CS pin is in a logic
low state.
WR Logic low level:
3.5.3 Direct Control Mode
Beside the use of the parallel µC compatible interface a
parallel direct control mode can be choosen. In this
mode the output OUT0...OUT7 can be directly
controlled via the inputs D0...D7 without the need for
additional logic signals. To activate this mode pin CS
and WR need to be connected to ground.
.
VCC
• Parallel input data at the pins D0 - D7 is written into
the input latches
WR Logic high level:
• The parallel input data is latched in the input
latches. Any changes at the pins D0 - D7 after the
low-to-high transition of WR do not affect the input
latches.
D0 ... D7 - Parallel input. Parallel data bits are fed into
the pins D0 ... D7. The data is written into the input
latches when WR is logic low.
VCC
P0
P1
P2
P3
P4
P5
P6
P7
Controller
VCC
CS
WR
D0
D1
D2
Output lines
D3
D4
D5
D6
D7
DIAG
Parallel
Interface
IC1
Figure 10 Parallel Direct Control
Datasheet
9
Version 2.0, 2009-07-28