ICE2QS01 Datasheet, PDF (9/17 Pages) Infineon Technologies AG – Quasi-resonant PWM Controller

Quasi-Resonant PWM Controller
ICE2QS01
Functional Description
detected zero-crossing to the switch-on of the main
switch t_delay, theoretically:
∆t
=
-T---^o---^s--^c
4
–
t_delay
[3]
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
τ_td
=
C_zc
⋅
-R-----^z--^c--¹----^â‹---R----^z--^c--²--
R_zc1 + R_zc2
[4]
3.3.1.3 Switch-on Determination
In the system, turn-on of the power switch depends on
the value of the up/down counter, the value of the zero-
crossing counter and the voltage at the ZC pin v_ZC.
Turn-on happens only when the value in the both
counters are the same and the voltage at the ZC is
lower than the threshold V_ZCT1. For comparison of the
values from both counters, a digital comparator is used.
Once these counters have the same value, the
comparator generates a signal which sets the on/off
flip-flop, only when the voltage v_ZC is lower than the
threshold V_ZCT1.
Another signal which may trigger the digital comparator
is the output of a T_sMax clock signal, which limits the
maximum off time to avoid the low-frequency
operation.
During active burst mode operation, the digital
comparator is disabled and no pulse will be generated.
3.3.2
Switch-off Determination
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor v_CS is applied to an internal current
measurement unit, and its output voltage v₁ is
compared with the regulation voltage v_reg. Once the
voltage v₁ exceeds the voltage v_REG, the output flip-flop
is reset. As a result, the main power switch is switched
off. The relationship between the v₁ and the v_cs is
described by:
v₁ = 3.3 ⋅ v_CS + 0.7
[5]
To avoid mistriggering caused by the voltage spike
across the shunt resistor after switch-on of the main
power switch, a 330ns leading edge blanking time
applies to output of the comparator.
3.3.3
Foldback Point Correction
In addition to the cycle-by-cylce primary current
limitation, the IC incorporats a foldback point
correction. The current limit on CS pin voltage is now a
time dependent one. If the mains input voltage is high,
the MOSFET on time will be short and the current limit
will be low. In such a way, the maximum output power
for the SMPS designed with ICE2QS01 will be nearly
constant against the variations of mains input voltage.
The current sense voltage limit versus the MOSFET
maximum on time is shown in Figure 5.
1
0 .8
0 .6
0 .4
0 .2
0
0
5
10
15
20
Ton(us)
Figure 5 Maximum current limit versus MOSFET maximum on time
Version 2.1
9
25
30
October 2007