ICE1PCS02_07 Datasheet, PDF (9/18 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

CCM-PFC
ICE1PCS02/G
Functional Description
3.4.2 Soft Over Current Control (SOC)
The IC is designed not to support any output power
that corresponds to a voltage lower than -0.73V at the
ISENSE pin. A further increase in the inductor current,
which results in a lower ISENSE voltage, will activate
the Soft Over Current Control (SOC). This is a soft
control as it does not directly switch off the gate drive
like the PCL. It acts on the nonlinear gain block to result
in a reduced PWM duty cycle.
3.4.3 Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 3 (ISENSE)
reaches -1.08V. This voltage is amplified by OP1 by a
factor of -1.43 and connected to comparator C2 with a
reference voltage of 1.5V as shown in Figure 8. A
deglitcher with 300ns after the comparator improves
noise immunity to the activation of this protection.
Full-wave
Rectifier
ISENSE
R2
I_INDUCTOR
R1
Current Limit
1.5V
1.43x
OP1
Deglitcher
C2
300ns _{Turn Off}
Driver
ICE1PCS02/G
3.5 Fixed Switching Frequency
ICE1PCS02/G has an internally fixed switching
frequency as opposed to the ICE1PCS01/G which can
be externally set. This frequency is trimmed to 65kHz
with an accuracy +/-7.7% at 25^oC.
3.6 Average Current Control
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure 9.
From
Full-wave
Retifier
L1
R7
R2
R1
ISENSE
Current Loop
ICOMP
C3
Current Loop
Compensation
OTA2
1.1mS
+/-50uA (linear range)
S2
4V
Fault
ICE1PCS02/G
D1
R3 ^Vout
C2
R4
GATE
voltage
proportional to
averaged
Inductor current
PWM
Comparator
C1
Gate
Driver
RQ
S
PWM Logic
Nonlinear
Gain
Input From
Voltage Loop
Figure 8 Peak Current Limit (PCL)
3.4.4 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.8V, or
equivalently V_OUT falls below 16% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V_IN for
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.
3.4.5 Over-Voltage Protection (OVP)
Whenever V_OUT exceeds the rated value by 5%, the
over-voltage protection OVP is active as shown in
Figure 6. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V_OUT.
Figure 9 Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2 Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
9). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4V in the event
of standby mode.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Version 1.2
9
06 Feb 2007